Semiconductor device and method of fabricating the same

ABSTRACT

After a first metal film and a first interlayer insulating film are deposited successively on an insulating film on a semiconductor substrate, a via hole is formed in the first interlayer insulating film. A second metal film is grown in the via hole to form a via contact composed of the second metal film, while a recessed portion is formed over the via contact in the via hole. A cap layer composed of a material different from the material of the first metal film is formed in the recessed portion. Then, the first metal film is patterned by using a mask pattern for forming a lower interconnect and a cap layer as a mask, whereby a lower interconnect is formed.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor device havingmultilayer wiring or interconnects and to a method of fabricating thesame.

[0002] To provide a semiconductor LSI device operable at a higher speedwith improved reliability, there has been developed a technique forforming an interconnect using copper (Cu) having lower resistance thanaluminium (Al) that has been used conventionally for interconnectformation.

[0003] To miniaturize the semiconductor LSI device, the number of layerscontained in a multilayer wiring or interconnect structure has beenincreased gradually.

[0004] Referring now to FIG. 16 showing a cross-sectional structure of aconventional semiconductor device, a description will be given to amethod of forming, by using a dual damascene method (Dual Damascene: AULSI WIRING TECHNOLOGY, C. W. Kannta et. al. Jun. 11-12 1991, VMICConference), an upper interconnect to be connected to a lowerinterconnect through a via contact above a semiconductor substrateformed with the lower interconnect.

[0005] First, a first interconnect groove 3 is formed in a firstinterlayer insulating film 2 on a semiconductor substrate 1. Then, alower interconnect 7 composed of a first adhesion layer 4, a first seedlayer 5, and a first copper plating layer 6 is formed in the firstinterconnect groove 3.

[0006] Next, a second interlayer insulating film 8 is deposited, maskedwith a mask pattern (not shown) formed on the second interlayerinsulating film 8, and subjected to dry etching for successively forminga via hole 9 and a second interconnect groove 10 in the secondinterlayer insulating film 8. Thereafter, a second adhesion layer 11 anda second seed layer 12 composed of a copper film are depositedsuccessively on the second interlayer insulating film 8 including theinner surfaces of the via hole 9 and the second interconnect groove 10.

[0007] Next, a second copper plating layer 13 is deposited on the secondseed layer 12 by electroplating using the second seed layer 12 as acathode for plating. Then, the portions of the second adhesion layer 11,the second seed layer 12, and the second copper plating layer 13 exposedon the second interlayer insulating film 8 are removed such that a viacontact 14 and an upper interconnect 15 each composed of the secondadhesion layer 11, the second seed layer 12, and the second copperplating layer 13 are formed.

[0008] With the increasing miniaturization of the semiconductor LSIdevice, however, the following problems are encountered by theconventional method of forming multilayer wiring or interconnects.

[0009] (1) Since the mask pattern for forming the via hole is inevitablydisplaced from the lower interconnect 7, the via contact 14 is alsodisplaced from the lower interconnect 7. Consequently, the contact areabetween the lower interconnect 7 and the via contact 14 decreases and afaulty connection occurs between the lower interconnect 7 and the viacontact 14. FIG. 16 shows the case where the via contact 14 is displacedfrom the lower interconnect 7 by the displacement size b.

[0010] (2) If the via hole 9 has a high aspect ratio, the top portion ofthe via hole 9 is clogged with the second copper plating layer 13 beforethe inner portion of the via hole 9 is filled with the second copperplating layer 13, since the speed at which the second copper platinglayer 13 grows adjacent the top portion of the via hole 9 is higher thanthe speed at which the second copper plating layer 13 grows adjacent thebottom of the via hole 9 during the formation of the second copperplating layer 13 by electroplating. As a result, a void is producedwithin the via hole 9 to cause a faulty connection between the lowerinterconnect 7 and the upper interconnect 15.

SUMMARY OF THE INVENTION

[0011] In view of the foregoing, it is therefore an object of thepresent invention to prevent a reduction in the contact area between thelower interconnect and the via contact even if a mask pattern isdisplaced and prevent a void from being produced within the via holeduring the formation of the via contact.

[0012] To attain the object, a first method of fabricating asemiconductor device according to the present invention comprises:

[0013] a first step of depositing a first metal film on an insulatingfilm on a semiconductor substrate; a second step of depositing a firstinterlayer insulating film on the first metal film; a third step offorming, on the first interlayer insulating film, a first mask patternhaving an opening over a region in which a via hole is to be formed,etching the first interlayer insulating film by using the first maskpattern as a mask, and thereby forming a via hole in the firstinterlayer insulating film; a fourth step of growing a second metal filmin the via hole to form a via contact composed of the second metal filmand forming a recessed portion over the via contact in the via hole; afifth step of forming, in the recessed portion, a cap layer composed ofa material different from a material composing the first metal film; asixth step of forming, on the first interlayer insulating film, a secondmask pattern covering a region in which a lower interconnect is to beformed, etching the first interlayer insulating film by using the secondmask pattern and the cap layer as a mask, and thereby patterning thefirst interlayer insulating film; a seventh step of etching the firstmetal film by using the cap layer and the patterned first interlayerinsulating film as a mask and thereby forming a lower interconnectcomposed of the first metal film; an eighth step of depositing a secondinterlayer insulating film over an entire surface of the semiconductorsubstrate; a ninth step of planarizing the second interlayer insulatingfilm and exposing the via contact or the cap layer; and a tenth step offorming, on the second interlayer insulating film, an upper interconnectto be connected to the via contact or the cap layer.

[0014] In accordance with the first method of fabricating asemiconductor device, the lower interconnect is formed by forming thecap layer composed of the material different from the material composingthe first metal film such that the top surface of the via contact iscovered therewith and patterning the first metal film by using the maskpattern for forming the lower interconnect and the cap layer as a mask.This ensures the formation of the lower interconnect over the entirebottom surface of the via contact covered with the cap layer even if themask pattern for forming the lower interconnect is displaced and therebyprevents a reduction in the contact area between the lower interconnectand the via contact.

[0015] Since the first method of fabricating a semiconductor devicegrows the second metal film on the region of the first metal filmcomposing the lower interconnect which is exposed in the via hole, thesecond metal film can be grown only from the bottom side of the viahole. This prevents the production of a void within the via hole duringthe formation of the via contact since the inner portion of the via holeis filled with the second metal film before the top portion of the viahole is clogged with the second metal film.

[0016] In the first method of fabricating a semiconductor device, thefirst metal film and the second metal film are preferably composed ofthe same material.

[0017] In the arrangement, the first metal film composing the lowerinterconnect is connected directly to the second metal film composingthe via contact. Accordingly, even if electromigration occurs atcontinuity, the lower interconnect or the via contact is prevented fromserving as a migration barrier which interrupts the movement of metalatoms. This prevents the breakage of the interconnect due to anexcessive or insufficient quantity of metal atoms adjacent the junctioninterface between the lower interconnect and the via contact.

[0018] In this case, the first metal film and the second metal film arepreferably composed of copper.

[0019] This reduces the resistance of each of the lower interconnectcomposed of the first metal film and the via contact composed of thesecond metal film.

[0020] In this case, the first step preferably includes the step offorming a first adhesion layer under the first metal film and forming asecond adhesion layer on the first metal film, the third step preferablyincludes the step of etching the first interlayer insulating film andthe second adhesion layer by using the first mask pattern as a mask andthereby forming the via hole in the first interlayer insulating film andin the second adhesion layer, and the seventh step preferably includesthe step of etching the second adhesion layer, the first metal film, andthe first adhesion layer by using the cap layer and the patterned firstinterlayer insulating film as a mask and thereby forming the lowerinterconnect composed of the first adhesion layer, the first metal film,and the second adhesion layer.

[0021] In the arrangement, the first adhesion layer is interposedbetween the first metal film composing the lower interconnect and theinsulating film and the second adhesion layer is interposed between thefirst metal film and the first interlayer insulating film. This improvesthe adhesion between the lower interconnect and the insulating film orthe first interlayer insulating film, while providing a directconnection between the first metal film composing the lower interconnectand the second metal film composing the via contact.

[0022] In the first method of fabricating a semiconductor device, thefirst step preferably includes the step of forming a first adhesionlayer under the first metal film and forming a second adhesion layer onthe first metal film and the seventh step preferably includes the stepof etching the second adhesion layer, the first metal film, and thefirst adhesion layer by using the cap layer and the patterned firstinterlayer insulating film as a mask and thereby forming the lowerinterconnect composed of the first adhesion layer, the first metal film,and the second adhesion layer.

[0023] In the arrangement, the first adhesion layer is interposedbetween the first metal film composing the lower interconnect and theinsulating film and the second adhesion layer is interposed between thefirst metal film and the first interlayer insulating film. This improvesthe adhesion between the lower interconnect and the insulating film orthe first interlayer insulating film, while preventing the first metalfilm composing the lower interconnect from being exposed in the via holeduring the formation of the via contact and thereby suppressing theoxidation of the first metal film, i.e., the lower interconnect.

[0024] Preferably, the first method of fabricating a semiconductordevice further comprises, between the third step and the fourth step,the step of performing plasma processing using an argon plasma or ahydrogen plasma with respect to a portion of the first metal filmexposed in the via hole.

[0025] The arrangement allows the removal of the oxide layer formed onthe surface of the portion of the first metal film exposed in the viahole and thereby accelerates the growth of the second metal film in thevia hole.

[0026] In the first method of fabricating a semiconductor device, thefourth step preferably includes the step of forming the via contact andthe recessed portion by growing the second metal film in the via holesuch that an upper portion of the via hole remains hollow.

[0027] The arrangement allows easy formation of the via contact and therecessed portion.

[0028] In the first method of fabricating a semiconductor device, thefourth step preferably includes the step of forming the via contact andthe recessed portion by growing the second metal film in the via holesuch that the via hole is filled completely with the second metal filmand then removing a portion of the second metal film formed in an upperportion of the via hole.

[0029] The arrangement ensures the formation of the via contact and therecessed portion.

[0030] In this case, the fourth step preferably includes the step ofremoving the portion of the second metal film formed in the upperportion of the via hole by chemical mechanical polishing.

[0031] The arrangement allows easy removal of the portion of the secondmetal film formed in the upper portion of the via hole by adjusting theetching rate for the second metal film to be higher than the etchingrate for the first interlayer insulating film.

[0032] In the first method of fabricating a semiconductor device, thefourth step preferably includes the step of growing the second metalfilm by electroplating.

[0033] The arrangement ensures the growth of the second metal film onthe region of the first metal film composing the lower interconnectwhich is exposed in the via hole.

[0034] In this case, the fourth step preferably includes the step ofgrowing the second metal film by using the first metal film as a cathodefor plating.

[0035] The arrangement allows easy growth of the second metal film.

[0036] In the first method of fabricating a semiconductor device, thefourth step preferably includes the step of growing the second metalfilm by electroless plating or CVD.

[0037] The arrangement ensures the growth of the second metal film onthe region of the first metal film composing the lower interconnectwhich is exposed in the via hole.

[0038] In the first method of fabricating a semiconductor device, thefirst metal film is preferably composed of copper and the cap layer ispreferably composed of tungsten, gold, silver, nickel, niobium, orparadium.

[0039] The arrangement ensures the use of the cap layer as a mask inpatterning the first metal film and thereby forming the lowerinterconnect.

[0040] In the first method of fabricating a semiconductor device, thefifth step preferably includes the step of forming the cap layer bysupplying, onto the semiconductor substrate, a reactive gas whichselectively reacts with the second metal film.

[0041] This allows easy formation of the cap layer.

[0042] In this case, the second metal film is preferably composed ofcopper and the reactive gas preferably contains silicon.

[0043] This ensures the formation of the cap layer composed of thecopper silicide.

[0044] In the first method of fabricating a semiconductor device, theninth step preferably includes the step of leaving at least a lowerportion of the cap layer and the tenth step preferably includes the stepof forming the upper interconnect by performing patterning, whileprotecting a top surface of the via contact with the remaining caplayer.

[0045] The arrangement prevents the removal of the top surface of thevia contact even if the mask pattern for forming the upper interconnectis displaced from the via contact.

[0046] In the first method of fabricating a semiconductor device, theninth step preferably includes the step of etching back the secondinterlayer insulating film and the cap layer to remove the cap layer andcause an upper portion of the via contact to protrude from a top surfaceof the second interlayer insulating film and the tenth step includes thestep of forming a third adhesion layer over the second interlayerinsulating film except for a top surface of the via contact, depositingsuccessively a third metal film composed of the same material ascomposing the second metal film and a fourth adhesion layer on a topsurface of the third adhesion layer including the top surface of the viacontact, patterning the third adhesion layer, the third metal film, andthe fourth adhesion layer, and thereby forming the upper interconnectcomposed of the third adhesion layer, the third metal film, and thefourth adhesion layer.

[0047] In the arrangement, the second metal film, i.e., the via contactand the third metal film composing the upper interconnect are composedof the same material and the via contact is connected directly to thethird metal film. Accordingly, even if electromigration occurs atcontinuity, the via contact or the upper interconnect is prevented fromserving as a migration barrier which interrupts the movement of metalatoms. This prevents the breakage of the interconnect due to anexcessive or insufficient quantity of metal atoms adjacent the junctioninterface between the upper interconnect and the via contact.

[0048] A second method of fabricating a semiconductor device accordingto the present invention comprises: a first step of depositing a firstmetal film on an insulating film on a semiconductor substrate; a secondstep of depositing a first interlayer insulating film on the first metalfilm; a third step of forming, on the first interlayer insulating film,a first mask pattern having an opening over a region in which a via holeis to be formed, etching the first interlayer insulating film by usingthe first mask pattern as a mask, and thereby forming a via hole in thefirst interlayer insulating film; a fourth step of growing a secondmetal film composed of a material different from a material composingthe first metal film to form a via contact composed of the second metalfilm; a fifth step of forming, on the first interlayer insulating film,a second mask pattern covering a region in which a lower interconnect isto be formed, etching the first interlayer insulating film by using thesecond mask pattern and the via contact as a mask, and therebypatterning the first interlayer insulating film; a sixth step of etchingthe first metal film by using the via contact and the patterned firstinterlayer insulating film as a mask to form a lower interconnectcomposed of the first metal film; a seventh step of depositing a secondinterlayer insulating film over the entire surface of the semiconductorsubstrate; an eighth step of planarizing the second interlayerinsulating film and exposing the via contact; and a ninth step offorming, on the second interlayer insulating film, an upper interconnectto be connected to the via contact.

[0049] In accordance with the second method of fabricating asemiconductor device, the lower interconnect is formed by forming thevia contact composed of the material different from the materialcomposing the first metal film and patterning the first metal film byusing the mask pattern for forming the lower interconnect and the viacontact as a mask. This ensures the formation of the lower interconnectover the entire bottom surface of the via contact even if the maskpattern for forming the lower interconnect is displaced and prevents areduction in the contact area between the lower interconnect and the viacontact.

[0050] Since the second method of fabricating a semiconductor devicegrows the second metal film on the region of the first metal filmcomposing the lower interconnect which is exposed in the via hole, thesecond metal film can be grown only from the bottom side of the viahole. This prevents the production of a void within the via hole duringthe formation of the via contact since the inner portion of the via holeis filled with the second metal film before the top portion of the viahole is clogged with the second metal film.

[0051] In the second method of fabricating a semiconductor device, thefirst metal film is preferably composed of copper and the second metalfilm is preferably composed of tungsten, gold, silver, nickel, niobium,or paradium.

[0052] The arrangement ensures the use of the via contact as a mask inpatterning the first metal film and thereby forming the lowerinterconnect.

[0053] In the second method of fabricating a semiconductor device, thefirst step preferably includes the step of forming a first adhesionlayer under the first metal film and forming a second adhesion layer onthe first metal film and the seventh step preferably includes the stepof etching the second adhesion layer, the first metal film, and thefirst adhesion layer by using the cap layer and the patterned firstinterlayer insulating film as a mask and thereby forming the lowerinterconnect composed of the first adhesion layer, the first metal film,and the second adhesion layer.

[0054] In the arrangement, the first adhesion layer is interposedbetween the first metal film composing the lower interconnect and theinsulating film and the second adhesion layer is interposed between thefirst metal film and the first interlayer insulating film. This improvesthe adhesion between the lower interconnect and the insulating film orthe first interlayer insulating film, while preventing the first metalfilm composing the lower interconnect from being exposed in the via holeduring the formation of the via contact and thereby suppressing theoxidation of the first metal film, i.e., the lower interconnect.

[0055] Preferably, the second method of fabricating a semiconductordevice further comprises, between the third step and the fourth step,the step of performing plasma processing using an argon plasma or ahydrogen plasma with respect to a portion of the first metal filmexposed in the via hole.

[0056] The arrangement allows the removal of the oxide layer formed onthe surface of the portion of the first metal film exposed in the viahole and thereby accelerates the growth of the second metal film in thevia hole.

[0057] In the second method of fabricating a semiconductor device, thefourth step preferably includes the step of forming the via contact bygrowing the second metal film in the via hole till a surface of thesecond metal film becomes higher in level than a surface of the firstinterlayer insulating film and then removing a portion of the secondmetal film higher in level than the surface of the first interlayerinsulating film.

[0058] The arrangement ensures the formation of the via contact.

[0059] In the second method of fabricating a semiconductor device, thefourth step preferably includes the step of growing the second metalfilm by electroplating.

[0060] The arrangement ensures the growth of the second metal film onthe region of the first metal film composing the lower interconnectwhich is exposed in the via hole.

[0061] In this case, the fourth step preferably includes the step ofgrowing the second metal film by using the first metal film as a cathodefor plating.

[0062] The arrangement allows easy growth of the second metal film.

[0063] In the second method of fabricating a semiconductor device, thefourth step preferably includes the step of growing the second metalfilm by electroless plating or CVD.

[0064] The arrangement ensures the growth of the second metal film onthe region of the first metal film composing the lower interconnectwhich is exposed in the via hole.

[0065] In the second method of fabricating a semiconductor device, thefourth step preferably includes the step of forming the second metalfilm by supplying, onto the semiconductor substrate, a reactive gaswhich selectively reacts with the first metal film.

[0066] The arrangement ensures easy growth of the second metal film onthe region of the first metal film composing the lower interconnectwhich is exposed in the via hole.

[0067] In this case, the first metal film is preferably composed ofcopper and the reactive gas preferably contains silicon.

[0068] This ensures the growth of the second metal film composed of thecopper silicide.

[0069] A semiconductor device according to the present inventioncomprises: a lower interconnect formed on a semiconductor substrate; aninterlayer insulating film deposited on the lower interconnect; a viacontact formed in the interlayer insulating film to be connected to thelower interconnect; and an upper interconnect formed on the interlayerinsulating film to be connected to the lower interconnect through thevia contact, the lower interconnect and the via contact being composedof the same material, the via contact being connected directly to a topsurface of the lower interconnect without extending off the top surfaceof the lower interconnect.

[0070] In the semiconductor device according to the present invention,the lower interconnect and the via contact are composed of the samematerial and the via contact is connected directly to the top surface ofthe lower interconnect. Accordingly, even if electromigration occurs atcontinuity, the lower interconnect or the via contact is prevented fromserving as a migration barrier which interrupts the movement of metalatoms. This prevents the breakage of the interconnect due to anexcessive or insufficient quantity of metal atoms adjacent the junctioninterface between the lower interconnect and the via contact.

BRIEF DESCRIPTION OF THE DRAWINGS

[0071] FIGS. 1(a) to 1(c) are cross-sectional views illustrating theindividual process steps of a method of fabricating a semiconductordevice according to a first embodiment;

[0072] FIGS. 2(a) to 2(c) are cross-sectional views illustrating theindividual process steps of the method of fabricating a semiconductordevice according to the first embodiment;

[0073] FIGS. 3(a) to 3(c) are cross-sectional views illustrating theindividual process steps of the method of fabricating a semiconductordevice according to the first embodiment;

[0074] FIGS. 4(a) to 4(c) are cross-sectional views illustrating theindividual process steps of the method of fabricating a semiconductordevice according to the first embodiment;

[0075]FIG. 5 illustrates the process of forming a via contact byselectively growing a copper film in a via hole by electroplating in themethod of fabricating a semiconductor device according to the firstembodiment;

[0076] FIGS. 6(a) and 6(b) are cross-sectional views illustrating theindividual process steps of a method of fabricating a semiconductordevice according to a first variation of the first embodiment;

[0077] FIGS. 7(a) and 7(b) are cross-sectional views illustrating theindividual process steps of a method of fabricating a semiconductordevice according to a second variation of the first embodiment;

[0078] FIGS. 8(a) to 8(c) are cross-sectional views illustrating theindividual process steps of a method of fabricating a semiconductordevice according to a second embodiment;

[0079] FIGS. 9(a) and 9(b) are cross-sectional views illustrating theindividual process steps of a method of fabricating a semiconductordevice according to a third embodiment;

[0080] FIGS. 10(a) and 10(b) are cross-sectional views illustrating theindividual process steps of the method of fabricating a semiconductordevice according to the third embodiment;

[0081] FIGS. 11(a) to 11(c) are cross-sectional views illustrating theindividual process steps of a method of fabricating a semiconductordevice according to a fourth embodiment;

[0082] FIGS. 12(a) to 12(c) are cross-sectional views illustrating theindividual process steps of the method of fabricating a semiconductordevice according to the fourth embodiment;

[0083] FIGS. 13(a) to 13(c) are cross-sectional views illustrating theindividual process steps of the method of fabricating a semiconductordevice according to the fourth embodiment;

[0084] FIGS. 14(a) and 14(b) are cross-sectional views illustrating theindividual process steps of the method of fabricating a semiconductordevice according to the fourth embodiment;

[0085] FIGS. 15(a) and 15(b) are cross-sectional views illustrating theindividual process steps of the method of fabricating a semiconductordevice according to a first variation of the fourth embodiment; and

[0086]FIG. 16 is a cross-sectional view of a conventional semiconductordevice.

DETAILED DESCRIPTION OF THE INVENTION EMBODIMENT 1

[0087] A semiconductor device and a method of fabricating the sameaccording to a first embodiment of the present invention will bedescribed with reference to the drawings.

[0088] FIGS. 1(a) to 1(c) , FIGS. 2(a) to 2(c) , FIGS. 3(a) to 3(c), andFIGS. 4(a) to 4(c) are cross-sectional views illustrating the individualprocess steps of the method of fabricating a semiconductor deviceaccording to the first embodiment.

[0089] First, as shown in FIG. 1(a), an insulating film 102 is depositedon a semiconductor substrate 101 that has been formed preliminarily witha semiconductor active element (not shown) Then, a first adhesion layer103 composed of, e.g., a tantalum alloy film, a first metal film 104composed of, e.g., a copper film, and a second adhesion layer 105composed of, e.g., a tantalum alloy film are formed successively on theinsulating film 102. Thereafter, a first interlayer insulating film 106composed of, e.g., a silicon oxide film is deposited on the secondadhesion layer 105.

[0090] The resulting multilayer thin film composed of the first adhesionlayer 103, the first metal film 104, and the second adhesion layer 105has a thickness of about 350 nm and the first interlayer insulating film106 has a thickness of about 1500 nm.

[0091] Next, a first resist pattern 107 having an opening over a regionin which a via hole is to be formed is formed on the first interlayerinsulating film 106. Subsequently, dry etching is performed successivelywith respect to the first interlayer insulating film 106 and the secondadhesion layer 105 by using the first resist pattern 107 as a mask,thereby forming a via hole 108 in the second adhesion layer 105 and inthe first interlayer insulating film 106, as shown in FIG. 1(b). Afterthat, the first resist pattern 107 is removed by ashing.

[0092] Next, as shown in FIG. 1(c), a second metal film, specifically acopper film, is grown selectively on a region of the first metal film104 exposed in the via hole 108 by using, e.g., electroplating, therebyforming a via contact 109 composed of the copper film. At this time, thecopper film is grown such that an upper portion of the via hole 108remains hollow, whereby a recessed portion 108 a having a depth of about300 nm is formed over the via contact 109 in the via hole 108. Thisallows easy formation of the via contact 109 and the recessed portion108 a.

[0093]FIG. 5 illustrates the process of forming the via contact 109 byselectively growing the copper film in the via hole 108 byelectroplating.

[0094] As shown in FIG. 5, the semiconductor substrate 101 is immersedin a plating solution 151 composed of a copper sulfate solutioncontaining a specified additive agent, which has been reserved in aplating tank (not shown). When a cathode electrode 152 of electroplatingequipment (not shown) is connected to the portion of the first metalfilm 104 exposed at a wafer edge of the semiconductor substrate 101,electrons are supplied from the cathode electrode 152 to the first metalfilm 104 so that the first metal film 104 serves as a cathode forplating. This allows selective deposition of the copper film on theregion of the first metal film 104 exposed in the via hole 108.

[0095] It is to be noted that the first and second adhesion layers 103and 105 are not depicted in FIG. 5.

[0096] Next, as shown in FIG. 2(a), a tungsten film is grown by, e.g.,selective CVD in the recessed portion 108 a to form a cap layer 110composed of the tungsten film.

[0097] Although the first embodiment has used selective CVD for theformation of the cap layer 110, it is also possible to form the caplayer 110 composed of the tungsten film in the recessed portion 108 a bya blanket tungsten process, in which a tungsten film is deposited on thefirst interlayer insulating film 106 including the recessed portion 108a and the portion of the tungsten film exposed on the first interlayerinsulating film 106 is removed.

[0098] Next, as shown in FIG. 2(b), the first interlayer insulating film106 is etched back by a thickness of about 1000 nm to have a thicknessof about 500 nm such that the via contact 109 and the cap layer 110protrude from the top surface of the first interlayer insulating film106. Then, a second resist pattern 111 is formed on the first interlayerinsulating film 106, the via contact 109, and the cap layer 110 to maska region in which a lower interconnect is to be formed. It is to benoted that FIG. 2(b) shows the case where the second resist pattern 111is displaced from the via contact 109 by a displacement size a1.

[0099] Next, as shown in FIG. 2(c), dry etching using a CF-containingetching gas for removing the oxide film is performed at a lowtemperature with respect to the first interlayer insulating film 106 byusing the second resist pattern 111 and the cap layer 110 as a mask,thereby patterning the first interlayer insulating film 106.

[0100] Next, as shown in FIG. 3(a), dry etching using a Cl-containingetching gas for removing the copper film and the tantalum-containingmetal film is performed successively with respect to the second adhesionlayer 105, the first metal film 104, and the first adhesion layer 103 byusing the cap layer 110 and the patterned first interlayer insulatingfilm 106 as a mask, thereby forming a lower interconnect 112 composed ofthe first adhesion layer 103, the first metal film 104, and the secondadhesion layer 105.

[0101] At this time, the cap layer 110 not only serves as an etchingstopper for dry etching using the CF-containing etching gas or theCl-containing etching gas but also remains even at the completion of dryetching. Consequently, the via contact 109 remains in a perfectconfiguration and the lower interconnect 112 is formed reliably over theentire bottom surface of the via contact 109.

[0102] Between the adjacent lower interconnects 112 on the semiconductorsubstrate 101, there is formed an interconnect gap 113.

[0103] Next, as shown in FIG. 3(b), dry etching using a CF-containingetching gas is performed with respect to the insulating film 102 byusing the cap layer 110 and the patterned first interlayer insulatingfilm 106 as a mask, thereby partially removing the region disposedbetween the adjacent lower interconnects 112 and in the upper portion ofthe insulating film 102 by about a thickness of 300 nm. After that, asecond interlayer insulating film 114 composed of a SiO₂ film isdeposited on the insulating film 102, the first interlayer insulatingfilm 106, the via contact 109, the cap layer 110, and the lowerinterconnect 112 by using a SiH₄/N₂O-containing gas plasma in, e.g.,plasma CVD equipment.

[0104] Since the step coverage of the SiO₂ film deposited by using theSiH₄/N₂O-containing gas plasma is poor, if the groove formed in theinterconnect gap 113 has a high aspect ratio, a void 113 a is producedwithin the interconnect gap 113 in the second interlayer insulating film114. If the groove formed in the interconnect gap 113 has a low aspectratio, a gap portion 113 b is formed internally of the second interlayerinsulating film 114 deposited over the wall surface and bottom portionof the groove.

[0105] In the present embodiment, it is preferable to remove, prior tothe deposition of the second interlayer insulating film 114, a copperoxide film formed on the side surfaces of the first metal film 104composing the lower interconnect 112 and the via contact 109 byperforming plasma processing using a hydrogen plasma or an ammoniaplasma with respect to the side surfaces of the first metal film 104 andthe via contact 109 and then deposit an extremely thin film of SiN,SiON, or the like for preventing reoxidization, though they are notdepicted in the drawings.

[0106] Next, as shown in FIG. 3(c), a third interlayer insulating film115 composed of a SiO₂ film is deposited over the entire surface of thesecond interlayer insulating film 114 including the gap portion 113 b byusing, e.g., high-density plasma (HDP) CVD equipment.

[0107] Since the step coverage of the SiO₂ film deposited by using thehigh-density plasma is excellent, the gap portion 113 b is filledcompletely with the third interlayer insulating film 115.

[0108] Since the second and third interlayer insulating films 114 and115 have been deposited such that the void 113 b is produced within theinterconnect gap 113 as shown in FIGS. 3(b) and 3(c), the specificinductive capacity, i.e., capacitance between the adjacent lowerinterconnects 112 can be reduced.

[0109] Next, as shown in FIG. 4(a), the cap layer 110 is removed and thethird interlayer insulating film 115 is planarized by, e.g., CMP suchthat the top surface of the via contact 109 is exposed.

[0110] At this time, since the top surface of the via contact 109 ishigher in level than the upper end of the first interlayer insulatingfilm 106, i.e., the upper end of the void 113 a, it is possible toadjust the top surface of the planarized third interlayer insulatingfilm 115 to be higher in level than the upper end of the void 113 a byhalting the polishing of the third interlayer insulating film 115 usingCMP at the top surface of the via contact 109, i.e., by using the viacontact 109 as an etching stopper. After the third interlayer insulatingfilm 115 is planarized by CMP, the void 113 a is prevented from formingan opening in the top surface of the planarized third interlayerinsulating film 115.

[0111] Next, as shown in FIG. 4(b), a third adhesion layer 116 composedof, e.g., a tantalum alloy film, a third metal film 117 composed of,e.g., a copper film, and a fourth adhesion layer 118 composed of, e.g.,a tantalum alloy film are formed successively on the top surface of thethird interlayer insulating film 115 including the top surface of thevia contact 109.

[0112] Next, a resist pattern (not shown) covering a region in which anupper interconnect is to be formed is formed on the fourth adhesionlayer 118. Then, dry etching is performed successively with respect tothe fourth adhesion layer 118, the third metal film 117, and the thirdadhesion layer 116 by using the resist pattern as a mask, therebyforming an upper interconnect 119 which is composed of the thirdadhesion layer 116, the third metal film 117, and the fourth adhesionlayer 118 and to be connected to the via contact 109, as shown in FIG.4(c).

[0113] Thus, according to the first embodiment, the lower interconnect112 is formed by forming the cap layer 110 composed of the materialdifferent from the material of the first metal film 104 such that thetop surface of the via contact 109 is covered therewith and patterningthe first metal film 104 by using the mask pattern for forming the lowerinterconnect and the cap layer 110 as a mask. Even when the mask patternfor forming the lower interconnect is displaced, the lower interconnect112 is formed reliably over the entire bottom surface of the via contact109 covered with the cap layer 110, so that a reduction in the contactarea between the lower interconnect 112 and the via contact 109 isprevented.

[0114] According to the first embodiment, it is also possible to growthe copper film only from the bottom side of the via hole 108 since thecopper film is grown on the region of the first metal film 104 composingthe lower interconnect 112 which is exposed in the via hole 108. Thisprevents the production of the void within the via hole 108 during theformation of the via contact 109 since the inner portion of the via hole108 is filled with the copper film before the top portion thereof isclogged with the copper film.

[0115] In addition, the first embodiment has used copper as the materialof each of the first metal film 104 composing the lower interconnect 112and the via contact 109 which is connected directly to the first metalfilm 104. If different metals are connected to each other in wiring andelectromigration occurs at continuity, one of the metals forms amigration barrier against the other of the metals to interrupt themovement of metal atoms. As a result, the wiring may be broken due to anexcessive or insufficient quantity of metal atoms adjacent the junctioninterface between the two metals. However, since the lower interconnect112 and the via contact 109 are composed of the same material andconnected directly to each other, the lower interconnect 112 or the viacontact 109 is prevented from serving as a migration barrier whichinterrupts the movement of metal atoms. This prevents the breakage ofthe wiring due to an excessive or insufficient quantity of metal atomsadjacent the junction interface between the lower interconnect 112 andthe via contact 109.

[0116] Moreover, since the first embodiment has interposed the firstadhesion layer 103 and the second adhesion layer 105 between the firstmetal film 104 composing the lower interconnect 112 and the insulatingfilm 102 and between the first metal film 104 and the first interlayerinsulating film 106, respectively, the adhesion between the lowerinterconnect 112 and the insulating film 102 or the first interlayerinsulating film 106 is improved.

[0117] Although the first embodiment has used copper as the material ofeach of the first metal film 104 and the via contact 109, another metalmay also be used as the material of each of the first metal film 104 andthe via contact 109 instead of copper.

[0118] Although the first embodiment has used electroplating in formingthe via contact 109, electroless plating, selective CVD, or like methodmay also be used instead of electroplating.

[0119] Although the first embodiment has used copper and tungsten as therespective materials of the first metal film 104 and the cap layer 110,it is also possible to use a combination of other different metals asthe respective materials of the first metal film 104 and the cap layer110 instead of copper and tungsten. Specifically, gold (Au), silver(Ag), nickel (Ni), platinum (Pt), niobium (Nb), paradium (Pd), or thelike may be used as the material of the cap layer 110 instead oftungsten if copper is used as the material of the first metal film 104.

[0120] Although the first embodiment has formed the first adhesion layer103 under the first metal film 104 and the second adhesion layer 105 onthe first metal film 104, the first or second adhesion layer 103 or 105may not be formed.

FIRST VARIATION OF EMBODIMENT 1

[0121] A method of fabricating a semiconductor device according to afirst variation of the first embodiment of the present invention will bedescribed with reference to the drawings.

[0122] FIGS. 6(a) and 6(b) are cross-sectional views illustrating theindividual process steps of the method of fabricating a semiconductordevice according to the first variation of the first embodiment.

[0123] The fabrication method of the first variation is different fromthat of the first embodiment in that the dry etching process using thefirst resist pattern 107 as a mask (see FIG. 1(a)) is performed onlywith respect to the first interlayer insulating film 106 to form the viahole 108 in the first interlayer insulating film 106, as shown in FIG.6(a), and then the via contact 109 is formed on the region of the secondadhesion layer 105 exposed in the via hole 108, as shown in FIG. 6(b).

[0124] The process steps subsequent to the step illustrated in FIG. 6(b)according to the first variation of the first embodiment are the same asthe process steps subsequent to the step illustrated in FIG. 2(a)according to the first embodiment except that the second adhesion layer105 is interposed between the first metal film 104 and the via contact109.

[0125] Since the first variation of the first embodiment prevents thefirst metal film 104 composing the lower interconnect 112 from beingexposed in the via hole 108 during the formation of the via contact 109,the oxidization of the first metal film 104 is suppressed so that thereliability of the lower interconnect 112 is improved.

SECOND VARIATION OF EMBODIMENT 1

[0126] A method of fabricating a semiconductor device according to asecond variation of the first embodiment of the present invention willbe described with reference to the drawings.

[0127] FIGS. 7(a) and 7(b) are cross-sectional views illustrating theindividual process steps of the method of fabricating a semiconductordevice according to the second variation.

[0128] The first aspect in which the fabrication method of the secondvariation is different from that of the first embodiment is that plasmaprocessing using an argon plasma or a hydrogen plasma is performed withrespect to the portion of the first metal film 104 exposed in the viahole 108 between the step of forming the via hole 108 (see FIG. 1(b))and the step of forming the via contact 109 (see FIG. 1(c)), therebyperforming the step of removing the oxide layer formed on the surface ofthe exposed portion.

[0129] The second aspect in which the fabrication method of the secondvariation is different from that of the first embodiment is that thestep of forming the via contact 109 (see FIG. 1(c)) includes growing thesecond metal film 109A (specifically a copper film) in the via hole 108such that the via hole 108 is filled completely with the second metalfilm 109A, as shown in FIG. 7(a)), and then removing the portion of thesecond metal film 109A formed in the upper portion of the via hole 108,as shown in FIG. 7(b), thereby forming the via contact 109 composed ofthe second metal film 109A and simultaneously forming a recessed portion108 a over the via contact 109 in the via hole 108.

[0130] It is to be noted that the process steps subsequent to the stepillustrated in FIG. 7(b) according to the second variation of the firstembodiment are the same as the process steps subsequent to the stepillustrated in FIG. 2(a) according to the first embodiment.

[0131] Since the second variation of the first embodiment has performedthe plasma processing with respect to the portion of the first metalfilm 104 exposed in the via hole 108 and thereby removed the oxide layerformed on the surface of the exposed portion, the growth of the secondmetal film 109A in the via hole 108 can be accelerated.

[0132] In addition, since the second variation of the first embodimenthas formed the via contact 109 and the recessed portion 108 a by growingthe second metal film 109A in the via hole 108 such that the via hole108 is filled completely with the second metal film 109A and thenremoving the portion of the second metal film 109A formed in the upperportion of the via hole 108, the via contact 109 and the recessedportion 108 a can be formed reliably.

[0133] In the second variation of the first embodiment, the portion ofthe second metal film 109A formed in the upper portion of the via hole108 is preferably removed by chemical mechanical polishing (CMP) in thestep illustrated in FIG. 7(b). If the etching rate for the second metalfilm 109A is adjusted to be higher than the etching rate for the firstinterlayer insulating film 106, the portion of the second metal film109A formed in the upper portion of the via hole 108 can be removedeasily by CMP. Specifically, if a copper film and a silicon oxide filmare used as the second metal film 109A and the first interlayerinsulating film 106, respectively, the portion of the second metal film109A formed in the upper portion of the via hole 108 is preferablyremoved by CMP using alumina or the like as a slurry.

THIRD VARIATION OF EMBODIMENT 1

[0134] A method of fabricating a semiconductor device according to athird variation of the first embodiment of the present invention will bedescribed with reference to the drawings.

[0135] The fabrication method of the third variation is different fromthat of the first embodiment in that, during the formation of the caplayer 110 on the via contact 109 (see FIG. 2(a)), a copper silicidelayer is formed selectively by exposing the top surface of the viacontact 109 to a gas containing silane at a high temperature of about400° C., whereby the cap layer 110 composed of the copper silicide layeris formed.

[0136] Since the third variation of the first embodiment has formed thecap layer 110 composed of the copper silicide layer by using the gascontaining silane which selectively reacts with copper composing the viacontact 109, the cap layer 110 can be formed easily.

[0137] Although the third variation of the first embodiment has formedthe cap layer 110 composed of the copper silicide layer by using the gascontaining silane, it is also possible to form the cap layer 110composed of an AlCu film by using another reactive gas which selectivelyreacts with copper such as TMAH (trimethylaluminum hydride).

EMBODIMENT 2

[0138] A method of fabricating a semiconductor device according to asecond embodiment of the present invention will be described withreference to the drawings.

[0139] Since the second embodiment performs the same process steps asillustrated in FIGS. 1(a) to 1(c), FIGS. 2(a) to 2(c), and FIGS. 3(a) to3(c) in accordance with the method of fabricating a semiconductor deviceof the first embodiment, the description will be given to the processsteps subsequent to the step illustrated in 3(c) with reference to FIGS.8(a) to 8(c).

[0140] First, as shown in FIG. 8(a), the upper portion of the cap layer110 is removed by, e.g., CMP and the third interlayer insulating film115 is planarized such that the top surface of the remaining cap layer110 is exposed.

[0141] Next, as shown in FIG. 8(b), a third adhesion layer 116 composedof, e.g., a tantalum alloy film, a third metal film 117 composed of,e.g., a copper film, and a fourth adhesion layer 118 composed of, e.g.,a tantalum alloy film are formed successively on the top surface of thethird interlayer insulating film 115 including the top surface of theremaining cap layer 110.

[0142] Next, a resist pattern (not shown) covering theupper-interconnect formation region is formed on the fourth adhesionlayer 118. Then, dry etching is performed successively with respect tothe fourth adhesion layer 118, the third metal film 117, and the thirdadhesion layer 116 by using the resist pattern as a mask, therebyforming the upper interconnect 119 which is composed of the thirdadhesion layer 116, the third metal film 117, and the fourth adhesionlayer 118 and to be connected to the via contact 109 through theremaining cap layer 110, as shown in FIG. 8(c). It is to be noted thatFIG. 8(c) illustrates the case where the resist pattern covering theupper-interconnect formation region, i.e., the upper interconnect 119 isdisplaced from the via contact 109 by the displacement size a2 and theremaining cap layer 110 is exposed.

[0143] The second embodiment achieves the following effect in additionto the effects achieved by the first embodiment.

[0144] That is, since the upper interconnect 119 has been formed byperforming patterning while protecting the top surface of the viacontact 109 with the cap layer 110, the removal of the top surface ofthe via contact 109 can be prevented even if the mask pattern forforming the upper interconnect is displaced from the via contact 109, sothat the reliability of the via contact 109 is improved.

EMBODIMENT 3

[0145] A method of fabricating a semiconductor device according to athird embodiment of the present invention will be described withreference to the drawings.

[0146] Since the third embodiment performs the same process steps asillustrated in FIGS. 1(a) to 1(c), FIGS. 2(a) to 2(c), FIGS. 3(a) to3(c), and FIG. 4(a) in accordance with the method of fabricating asemiconductor device of the first embodiment, the description will begiven to the process steps subsequent to the step illustrated in FIG.4(a) with reference to FIGS. 9(a) and 9(b) and FIGS. 10(a) and 10(b).

[0147] First, as shown in FIG. 9(a), wet etching is performed by way ofexample with respect to the third interlayer insulating film 115,thereby causing the upper portion of the via contact 109 to protrudefrom the top surface of the third interlayer insulating film 115. Then,the third adhesion layer 116 composed of, e.g., a tantalum alloy film isdeposited on the top surface of the third interlayer insulating film 115including the top surface of the via contact 109.

[0148] Next, as shown in FIG. 9(b), the third adhesion layer 116 isplanarized by, e.g., CMP such that the top surface of the via contact109 is exposed. Then, as shown in FIG. 10(a), the third metal film 117composed of, e.g., a copper film and the fourth adhesion layer 118composed of, e.g., a tantalum alloy film are deposited sequentially onthe top surface of the third adhesion layer 116 including the topsurface of the via contact 109.

[0149] Next, a resist pattern (not shown) covering the upperinterconnect formation region is formed on the fourth adhesion layer118. Then, dry etching is performed successively with respect to thefourth adhesion layer 118, the third metal film 117, and the thirdadhesion layer 116 by using the resist pattern as a mask, therebyforming the upper interconnect 119 which is composed of the thirdadhesion layer 116, the third metal film 117, and the fourth adhesionlayer 118 and to be connected to the via contact 109, as shown in FIG.10(b).

[0150] According to the third embodiment, the following effect isachieved in addition to the effects achieved by the first embodiment.

[0151] That is, copper is used as the material of the third metal film117 composing the via contact 109 and the upper interconnect 119 and thevia contact 109 is connected directly to the third metal film 117.Accordingly, even if electromigration occurs at continuity, the viacontact 109 or the upper interconnect 119 is prevented from serving as amigration barrier which interrupts the movement of metal atoms. Thisprevents the breakage of the wiring due to an excessive or insufficientquantity of metal atoms adjacent the junction interface between the viacontact 109 and the upper interconnect 119.

[0152] Although the third embodiment has used copper as the material ofeach of the via contact 109 and the third metal film 117, it is alsopossible to use another metal as the material of each of the via contact109 and the third metal film 117.

EMBODIMENT 4

[0153] A method of fabricating a semiconductor device according to afourth embodiment of the present invention will be described withreference to the drawings.

[0154] FIGS. 11(a) to 11(c), FIGS. 12(a) to 12(c), FIGS. 13(a) to 13(c),and FIGS. 14(a) and 14(b) are cross-sectional views illustrating theindividual process steps of the method of fabricating a semiconductordevice according to the fourth embodiment.

[0155] First, as shown in FIG. 11(a), an insulating film 202 isdeposited on a semiconductor substrate 201 that has been formedpreliminarily with a semiconductor active element (not shown) Then, afirst adhesion layer 203 composed of, e.g., a tantalum alloy film, afirst metal film 204 composed of, e.g., a copper film, and a secondadhesion layer 205 composed of, e.g., a tantalum alloy film are formedsuccessively on the insulating film 202. Thereafter, a first interlayerinsulating film 206 composed of, e.g., a silicon oxide film is depositedon the second adhesion layer 205.

[0156] The resulting multilayer thin film composed of the first adhesionlayer 203, the first metal film 204, and the second adhesion layer 205has a thickness of about 350 nm and the first interlayer insulating film206 has a thickness of about 1500 nm.

[0157] Next, a first resist pattern 207 having an opening over thevia-hole formation region is formed on the first interlayer insulatingfilm 206. Subsequently, dry etching is performed successively withrespect to the first interlayer insulating film 206 and the secondadhesion layer 205 by using the first resist pattern 207 as a mask,thereby forming a via hole 208 in the second adhesion layer 205 and inthe first interlayer insulating film 206, as shown in FIG. 11(b). Afterthat, the first resist pattern 207 is removed by ashing.

[0158] Next, as shown in FIG. 11(c), a second metal film, specifically atungsten film, is grown selectively on a region of the first metal film204 exposed in the via hole 208 by, e.g., electroplating, therebyforming a via contact 209 composed of the tungsten film. At this time,the first metal film 204 is used as the cathode for plating.

[0159] Next, as shown in FIG. 12(a), the first interlayer insulatingfilm 206 is etched back by a thickness of about 1000 nm to have athickness of about 500 nm such that the via contact 209 protrudes fromthe top surface of the first interlayer insulating film 206. Then, asecond resist pattern 210 is formed on the first interlayer insulatingfilm 206 and the via contact 209 to mask the lower-interconnectformation region. It is to be noted that FIG. 12(a) shows the case wherethe second resist pattern 210 is displaced from the via contact 209 bythe displacement size a3.

[0160] Next, as shown in FIG. 12(b), dry etching using a CF-containingetching gas for removing the oxide film is performed at a lowtemperature with respect to the first interlayer insulating film 206 byusing the second resist pattern 210 and the via contact 209 as a mask,thereby patterning the first interlayer insulating film 206.

[0161] Next, as shown in FIG. 12(c), dry etching using a Cl-containingetching gas for removing the copper film and the tantalum-containingmetal film is performed successively with respect to the second adhesionlayer 205, the first metal film 204, and the first adhesion layer 203 byusing the via contact 209 and the patterned first interlayer insulatingfilm 206 as a mask, thereby forming a lower interconnect 211 composed ofthe first adhesion layer 203, the first metal film 204, and the secondadhesion layer 205.

[0162] At this time, the via contact 209 serves as an etching stopperfor dry etching using the CF-containing etching gas or the Cl-containingetching gas so that the lower interconnect 211 is formed reliably overthe entire bottom surface of the via contact 209.

[0163] Between the adjacent lower interconnects 211 on the semiconductorsubstrate 201, there is formed an interconnect gap 212.

[0164] Next, as shown in FIG. 13(a), dry etching using a CF-containingetching gas is performed with respect to the insulating film 202 byusing the via contact 209 and the patterned first interlayer insulatingfilm 206 as a mask, thereby partially removing the region disposedbetween the adjacent lower interconnect 211 and in the upper portion ofthe insulating film 202 by about a thickness of 300 nm. After that, asecond interlayer insulating film 213 composed of a SiO₂ film isdeposited on the insulating film 202, the first interlayer insulatingfilm 206, the via contact 209, and the lower interconnect 211 by using aSiH₄/N₂O-containing gas plasma in, e.g., plasma CVD equipment.

[0165] Since the step coverage of the SiO₂ film deposited by using theSiH₄/N₂O-containing gas plasma is poor, if the groove formed in theinterconnect gap 212 has a high aspect ratio, a void 212 a is producedwithin the interconnect gap 212 in the second interlayer insulating film213. If the groove formed in the interconnect gap 212 has a low aspectratio, a gap portion 212 b is formed internally of the second interlayerinsulating film 213 deposited over the wall surface and bottom portionof the groove.

[0166] In the present embodiment, it is preferable to remove, prior tothe deposition of the second interlayer insulating film 213, a metaloxide film formed on the side surfaces of the first metal film 204composing the lower interconnect 211 and the via contact 209 byperforming plasma processing using a hydrogen plasma or an ammoniaplasma with respect to the side surfaces of the first metal film 204 andthe via contact 209 and then deposit an extremely thin film of SiN,SiON, or the like for preventing reoxidization, though they are notdepicted in the drawings.

[0167] Next, as shown in FIG. 13(b), a third interlayer insulating film214 composed of a SiO₂ film is deposited over the entire surface of thesecond interlayer insulating film 213 including the gap portion 212 b byusing, e.g., high-density plasma (HDP) CVD equipment.

[0168] Since the step coverage of the SiO₂ film deposited by using thehigh-density plasma is excellent, the gap portion 212 b is filledcompletely with the third interlayer insulating film 214.

[0169] Since the second and third interlayer insulating films 213 and214 have been deposited such that the void 212 a is produced within theinterconnect gap 212 as shown in FIGS. 13(a) and 13(b), the specificinductive capacity, i.e., capacitance between the adjacent lowerinterconnects 211 can be reduced.

[0170] Next, as shown in FIG. 13(c), the third interlayer insulatingfilm 214 is planarized by, e.g., CMP such that the via contact 209 isexposed.

[0171] At this time, since the top surface of the via contact 209 ishigher in level than the upper end of the first interlayer insulatingfilm 206, i.e., the upper end of the void 212 a, it is possible toadjust the top surface of the planarized third interlayer insulatingfilm 214 to be higher in level than the upper end of the void 212 a byhalting the polishing of the third interlayer insulating film 214 usingCMP at the top surface of the via contact 209, i.e., by using the viacontact 209 as an etching stopper. After the third interlayer insulatingfilm 214 is planarized by CMP, the void 212 a is prevented from formingan opening in the top surface of the planarized third interlayerinsulating film 214.

[0172] Next, as shown in FIG. 14(a), a third adhesion layer 215 composedof, e.g., a tantalum alloy film, a third metal film 216 composed of,e.g., a copper film, and a fourth adhesion layer 217 composed of, e.g.,a tantalum alloy film are formed successively on the top surface of thethird interlayer insulating film 214 including the top surface of thevia contact 209.

[0173] Next, a resist pattern (not shown) covering theupper-interconnect formation region is formed on the fourth adhesionlayer 217. Then, dry etching is performed successively with respect tothe fourth adhesion layer 217, the third metal film 216, and the thirdadhesion layer 215 by using the resist pattern as a mask, therebyforming the upper interconnect 218 which is composed of the thirdadhesion layer 215, the third metal film 216, and the fourth adhesionlayer 217 and to be connected to the via contact 209, as shown in FIG.14(b).

[0174] Thus, according to the fourth embodiment, the lower interconnect211 is formed by forming the via contact 209 composed of the materialdifferent from the material of the first metal film 204 and patterningthe first metal film 204 by using the mask pattern for forming the lowerinterconnect and the via contact 209 as a mask. Even when the maskpattern for forming the lower interconnect is displaced, the lowerinterconnect 211 is formed reliably over the entire bottom surface ofthe via contact 209, so that a reduction in the contact area between thelower interconnect 211 and the via contact 209 is prevented.

[0175] According to the fourth embodiment, it is also possible to growthe tungsten film only from the bottom side of the via hole 208 sincethe tungsten film is grown on the region of the first metal film 204composing the lower interconnect 211 which is exposed in the via hole208. This prevents the production of the void within the via hole 208during the formation of the via contact 209 since the inner portion ofthe via hole 208 is filled with the tungsten film before the top portionthereof is clogged with the tungsten film.

[0176] In addition, the step of forming the cap layer can be omittedaccording to the fourth embodiment. Accordingly, the lower interconnect211 can be formed easily compared with the case (see the firstembodiment) where the cap layer composed of a material different fromthe material of the first metal film 204 is formed to cover the topsurface of the via contact 209 and then the first metal film 204 ispatterned to form the lower interconnect 211 by using the cap layer as amask.

[0177] Moreover, since the fourth embodiment has interposed the firstadhesion layer 203 and the second adhesion layer 205 between the firstmetal film 204 composing the lower interconnect 211 and the insulatingfilm 202 and between the first metal film 204 and the first interlayerinsulating film 206, respectively, the adhesion between the lowerinterconnect 211 and the insulating film 202 or the first interlayerinsulating film 206 is improved.

[0178] Although the fourth embodiment has used copper and tungsten asthe respective materials of the first metal film 204 and the via contact209, a combination of other different metals may also be used as therespective materials of the first metal film 204 and the via contact 209instead of copper and tungsten. Specifically, gold (Au), silver (Ag),nickel (Ni), platinum (Pt), niobium (Nb), paradium (Pd), or the like maybe used as the material of the via contact 209 instead of tungsten ifcopper is used as the material of the first metal film 204.

[0179] Although the fourth embodiment has used electroplating in formingthe via contact 209, electroless plating, selective CVD, or like methodmay also be used instead of electroplating.

[0180] Although the fourth embodiment has formed the first adhesionlayer 203 under the first metal film 204 and the second adhesion layer205 on the first metal film 204, the first or second adhesion layer 203or 205 may not be formed.

[0181] In the fourth embodiment, plasma processing using an argon plasmaor a hydrogen plasma may also be performed with respect to the portionof the first metal film 204 exposed in the via hole 208 between the stepof forming the via hole 208 (see FIG. 10(b)) and the step of forming thevia contact 209 (see FIG. 10(c)). The plasma processing removes theoxide layer formed on the surface of the portion of the first metal film204 exposed in the via hole 208 and thereby accelerates the growth ofthe second metal film (metal film for forming the via contact 209) inthe via hole 208.

[0182] In the fourth embodiment, the step of forming the via contact 209(see FIG. 10(c)) may also be performed by growing the second metal filmin the via hole 208 till the surface of the second metal film is higherin level than at least the surface of the first interlayer insulatingfilm 206 and then removing the portion of the second metal film which ishigher in level than the surface of the first interlayer insulating film206, thereby forming the via contact 209. This ensures the formation ofthe via contact 209.

FIRST VARIATION OF EMBODIMENT 4

[0183] A method of fabricating a semiconductor device according to afirst variation of the fourth embodiment of the present invention willbe described with reference to the drawings.

[0184] FIGS. 15(a) and 15(b) are cross-sectional views illustrating theindividual process steps of the method of fabricating a semiconductordevice according to the first variation of the fourth embodiment.

[0185] The fabrication method of the first variation is different fromthat of the fourth embodiment in that the dry etching process using thefirst resist pattern 207 as a mask (see FIG. 11(a)) is performed onlywith respect to the first interlayer insulating film 206 to form the viahole 208 in the first interlayer insulating film 206, as shown in FIG.15(a), and then the via contact 209 is formed on the region of thesecond adhesion layer 205 exposed in the via hole 208, as shown in FIG.15(b).

[0186] The process steps subsequent to the step illustrated in FIG.15(b) according to the first variation of the fourth embodiment are thesame as the process steps subsequent to the step illustrated in FIG.12(a) according to the fourth embodiment except that the second adhesionlayer 205 is interposed between the first metal film 204 and the viacontact 209.

[0187] Since the first variation of the fourth embodiment prevents thefirst metal film 204 composing the lower interconnect 211 from beingexposed in the via hole 208 during the formation of the via contact 209,the oxidization of the first metal film 204 is suppressed so that thereliability of the lower interconnect 211 is improved.

SECOND VARIATION OF EMBODIMENT 4

[0188] A method of fabricating a semiconductor device according to asecond variation of the fourth embodiment of the present invention willbe described with reference to the drawings.

[0189] The fabrication method of the second variation is different fromthat of the fourth embodiment in that the step (see FIG. 11(c)) offorming the via contact 209 on the region of the first metal film 204exposed in the via hole 208 is performed by exposing the top surface ofthe first metal film 204 to a gas containing silane at a hightemperature of about 400° C., thereby forming the via contact 209composed of a copper silicide layer.

[0190] Since the second variation of the fourth embodiment has formedthe via contact 209 composed of the copper silicide layer by using thegas containing silane which selectively reacts with the first metal film204, i.e., the copper film, the via contact 209 can be formed easily.

[0191] Although the second variation of the fourth embodiment has formedthe via contact 209 composed of the copper silicide layer by using thegas containing silane, another reactive gas which selectively reactswith copper, such as TMAH (trimethylaluminum hydride), may also be usedto form the via contact 209 composed of an AlCu film.

What is claimed is:
 1. A semiconductor device comprising: a lowerinterconnect formed on a semiconductor substrate; an interlayerinsulating film deposited on the lower interconnect; a via contactformed in the interlayer insulating film to be connected to the lowerinterconnect; and an upper interconnect formed on the interlayerinsulating film to be connected to the lower interconnect through thevia contact, the lower interconnect and the via contact being composedof the same material, the via contact being connected directly to a topsurface of the lower interconnect without extending off the top surfaceof the lower interconnect.